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Elektronika MK-90 - hardware

UPDATE: The information shown here was initially obtained through reverse engineering and therefore may differ from the contents of recently published (2011/12/22) original datasheets.

Circuit diagrams

CPU board

System board


Keyboard controller and address decoder КА1835ВГ1

This chip returns the keyboard scan code (row and column of a pressed key) through the Channel 2 of the serial bus controller КА1835ВГ4. Pressing a key also causes an interrupt request to the vector at address $00C8.


LCD and memory controller КА1835ВГ3

This chip transfers display data from the RAM to the LCD drivers КА1835ИД1.

$E800 - address register, word size, write-only
This register specifies the starting address of the display memory.
$E802 - configuration register, word size, write-only
This register is initialised with a fixed value $88C6.
$E804 - lower byte of the address register
$E806 - lower byte of the configuration register

I/O device controller КА1835ВГ4

The controller supports eight serial channels, out of which four are used in the MK-90. All devices hooked on the bus share common DATA and SELECT lines, but use separate CLK signals.

Channel 0 and 1 are used by the SMP memory modules.
Channel 2 is used by the keyboard controller КА1835ВГ1.
The CLK output of the channel 3 drives the piezo buzzer.

$E810 - data register, byte size
Data written is serially transmitted through the serial bus.
Reading returns the contents of the shift register, then the next byte is shifted in from the serial bus.
$E812 - transfer rate register, word size
This register specifies the frequency of the CLK signal.
frequency = 800kHz / register_value
$E814 - control and status register, byte size
Function of individual bits when written
bits 2-0 select the serial channel
bit 3 specifies the transfer direction: 0=input, 1=output
Setting the transfer direction to input causes a byte to be read from the serial bus to the shift register.
cleared bit 4 enables external interrupts (i.e. CLK signal in the slave mode) to the vector $00C8, lowest priority
cleared bit 5 enables interrupts from the data register to the vector $00C4
cleared bit 6 enables interrupts from the INRT input to the vector $00C0, highest priority
bit 7 selects the transfer mode (i.e. which device drives the CLK line): 0=slave, 1=master
Function of individual bits when read
bits 1-0 are cleared
bit 2 returns the state of the RA line
bit 3 returns the state of the SELECT line
bits 6-4 return the values written to the interrupt enable bits
bit 7 is set when the data register is ready to be read/written
$E816 - command register, byte size
Writing to this register activates the SELECT signal, then the written byte is serially transmitted through the serial bus or a byte is read from the serial bus to the shift register, depending on the bit 3 of the register $E814.
Reading returns the contents of the shift register and deactivates the SELECT signal.

System controller КА1835ВГ5

$E81A - configuration register RG1, word size
$E81C - configuration register RG2, word size

Real time clock КА512ВИ1

It's a direct equivalent of the of the MC146818 real time clock. A 32768Hz crystal oscillator is used as the time base.
The Square Wave Output SQW drives the EVNT interrupt input (vector $0040) with a default frequency of 32Hz.
The Interrupt Request Output IRQ drives the INRT interrupt input (vector $00C0).

The chip bus lines AD0-AD7 are connected to the system bus lines AD1-AD8. Therefore any data written to the chip have to be shifted left by one bit, and any data read from the chip have to be shifted right by one bit. Also the chip registers are selected by consecutive even addresses.

The chip occupies the address range $EA00-$EA7E.

The pins of the КА512ВИ1 and the MC146818 are named differently. Here's a table of equivalent pin names:

КА512ВИ1MC146818
GN1,GN2OSC1,OSC2
AD0-AD7AD0-AD7
OVVSS
SECE
MACAS
RD/WRR/W
CDDS
SRRESET
RQINRIRQ
SEDCKFS
SYN1CKOUT
FLPS
SYN2SQW
UVDD

Miscellaneous